BIOS IT Blog
AMD EPYC™ Processor Enhanced Cache and Memory Architecture Whitepaper
The original AMD EPYC processor launched in 2017 as a revolutionary multi-die-on-package processor that allowed AMD to build a high performance and high throughput processor in a more efficient manner. Building off the success of the first generation, AMD has evolved the multi-die strategy, as the company now focused on a different form of multi-die packaging solutions in the second generation EPYC server processor.
This new solution, which AMD refers to as hybrid multi-die, allows AMD to not only divide a potentially large die into small interconnected dies, but also specific functions can be fabricated in the most appropriate process node based on required cost and performance. This agile hybrid multi-die architecture decoupled the CPU and cache complex and I/O innovation paths, giving AMD the ability to deliver the best process technology for CPU cores and letting I/O circuitry develop at its own rate. With this new architecture, to date AMD has been able to set over 140 world records across workloads that include Analytics and Big Data; Enterprise; HPC; Virtualization and Cloud Workloads.
This paper looks at the changes made from the first generation 7001 EPYC processor that improved cache performance and reduced overall memory access time variability and the latest 7002 gen processor. Please enter your email address to download the whitepaper. To download, fill out your email address in the form below.
Not what you're looking for? Check out our archives for more content